The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to semiconductor devices and their manufacture involving techniques for forming circuitry.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. These advancements have been accompanied by, and sometimes driven by, an increased demand for faster operation, reduction in cost, and higher reliability of semiconductor devices. The ability to form structures in increasingly smaller areas having increasingly dense circuitry, as well as the ability to place more semiconductor chips on a wafer, are important for meeting these and other needs of advancing technologies.
One aspect of semiconductor manufacture includes the formation of bond pads on a chip. The bond pads are normally placed on the periphery of the semiconductor chip, without underlying circuitry, and are used for subsequent wire bonding to a wafer. However, it is desirable to form bond pads over active circuitry in order to reduce the size of the chip. By reducing the size of the chip, more chips can be bonded to a wafer in a given area.
In such efforts to increase circuit and die densities, semiconductor device manufacture has encountered difficulty in the formation of metal pads over and near circuitry in the device. One such difficulty involves the production of a reliable product. Reliability concerns can prevent the placement of bond pads over active circuitry. For example, existing methods for forming pads over circuitry can produce cracking in underlying inter-metal oxide (IMO) layers. In addition, those methods that meet reliability goals are often too costly to be profitable.
One method for making reliable bond pads over active circuitry includes adding an additional passivation layer of sufficient thickness and an additional metal layer serving as the metal for wire bonding. Both the additional IMO layer and the metal layer should be thick enough to absorb and/or distribute the bonding force in such a way as to not crack the underlying IMO layers. A thickness of 1-2 microns for both the added passivation and metal layer has been found to prevent IMO cracking. However, the addition of a thick passivation layer and a thick metal layer is very costly as two mask steps are required, one for the via etch and one for the metal etch. Moreover, the throughput for the thick layers is low, which reduces the efficiency of the manufacturing process and results in higher product cost.
Obtaining a thick IMO layer has been achieved by leaving one or more metal layers inactive in a multi-metal chip. IMO thickness of greater than 2 microns can easily be realized by leaving one or more metal layers inactive. However, forming thick pad metallization is also desirable, but difficult to achieve, as design rules and processing constraints of the top metal layer typically prohibit making the layer significantly thicker than 1 micron. These and other problems associated with existing methods for bonding over active circuits are impediments to the growth and improvement of semiconductor technologies.
The present invention is directed to a semiconductor device with metal bond pads over active circuitry, and is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment of the present invention, a metal bond pad is formed on a semiconductor chip. The metal bond pad has a first metal pad layer, a TiN diffusion layer over the first metal pad layer, and a second metal pad layer over the TiN diffusion layer. A passivation layer is formed over the pad and subsequently etched to expose the second metal pad layer.
In still another example embodiment of the present invention, a system is arranged for manufacturing a semiconductor chip having a metal bond pad over active circuitry. A first metal deposition arrangement is adapted to deposit a metal bond pad on the circuit side, and a second metal deposition arrangement is adapted to deposit a metal layer over the circuit side. After the metal layer is deposited, a photoresist deposition arrangement is adapted to pattern a photoresist mask over the metal layer, and an etching arrangement is adapted to etch the circuit side and remove the portion of the metal layer not masked with the photoresist. When the circuit side has been etched, a photoresist removal arrangement is adapted to remove the photoresist.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description which follow more particularly exemplify these embodiments.